SV

Shekaripuram V. Venkatesh

CS Cadence Design Systems: 1 patents #18 of 77Top 25%
📍 Los Altos, CA: #168 of 419 inventorsTop 45%
🗺 California: #7,981 of 26,868 inventorsTop 30%
Overall (2005): #101,161 of 245,428Top 45%
1
Patents 2005

Issued Patents 2005

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6877143 System and method for timing abstraction of digital logic circuits Robert J. Palermo, Karem A. Sakallah, Mohammad Mortazavi 2005-04-05