Issued Patents 2005
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6947331 | Method of erasing an EEPROM cell utilizing a frequency/time domain based erased signal | Vladislav Vashchenko, Peter J. Hopper | 2005-09-20 |
| 6903978 | Method of PMOS stacked-gate memory cell programming enhancement utilizing stair-like pulses of control gate voltage | Vladislav Vashchenko, Peter J. Hopper | 2005-06-07 |
| 6903979 | Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of substrate current | Vladislav Vashchenko, Peter J. Hopper, Douglas Brisbin | 2005-06-07 |
| 6861306 | Method of forming a split-gate memory cell with a tip in the middle of the floating gate | Peter J. Hopper | 2005-03-01 |
| 6862216 | Non-volatile memory cell with gated diode and MOS transistor and method for using such cell | Peter J. Hopper, Vladislav Vashchenko | 2005-03-01 |