Issued Patents 2005
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6972995 | Imaging cell with a non-volatile memory that provides a long integration period and method of operating the imaging cell | Philipp Lindorfer, Vladislav Vashchenko, Wendy Greig | 2005-12-06 |
| 6972457 | Imaging cell that has a long integration period and method of operating the imaging cell | Philipp Lindorfer, Vladislav Vashchenko, Robert Drury | 2005-12-06 |
| 6970335 | LVTSCR ESD protection clamp with dynamically controlled blocking junction | Vladislav Vashchenko, Ann Concannon, Marcel ter Beek | 2005-11-29 |
| 6964907 | Method of etching a lateral trench under an extrinsic base and improved bipolar transistor | Alexei Sadovnikov, Vladislav Vashchenko, Peter Johnson | 2005-11-15 |
| 6963091 | Spin-injection devices on silicon material for conventional BiCMOS technology | Vladislav Vashchenko, Michael Mian | 2005-11-08 |
| 6958194 | Imager with improved sensitivity | Philipp Lindorfer, Michael Mian, Robert Drury | 2005-10-25 |
| 6956269 | Spin-polarization of carriers in semiconductor materials for spin-based microelectronic devices | Vladislav Vashchenko, Michael Mian | 2005-10-18 |
| 6952039 | ESD protection snapback structure for overvoltage self-protecting I/O cells | Vladislav Vashchenko, Ann Concannon, Marcel ter Beek | 2005-10-04 |
| 6946690 | High holding voltage ESD protection structure and method | Vladislav Vashchenko, Ann Concannon | 2005-09-20 |
| 6947331 | Method of erasing an EEPROM cell utilizing a frequency/time domain based erased signal | Yuri Mirgorodski, Vladislav Vashchenko | 2005-09-20 |
| 6940133 | Integrated trim structure utilizing dynamic doping | Philipp Lindorfer, Vladislav Vashchenko, Robert Drury | 2005-09-06 |
| 6933588 | High performance SCR-like BJT ESD protection structure | Vladislav Vashchenko, Ann Concannon, Marcel ter Beek | 2005-08-23 |
| 6933562 | Power transistor structure with non-uniform metal widths | Philipp Lindorfer, Vladislav Vashchenko, Andy Strachan | 2005-08-23 |
| 6924167 | Method of forming a bandgap tuned vertical color imager cell | Philipp Lindorfer | 2005-08-02 |
| 6919588 | High-voltage silicon controlled rectifier structure with improved punch through resistance | Vladislav Vashchenko, Andy Strachan, Philipp Lindorfer | 2005-07-19 |
| 6911679 | LVTSCR with compact design | Vladislav Vashchenko, Ann Concannon, Marcel ter Beek | 2005-06-28 |
| 6906357 | Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection | Vladislav Vashchenko, Marcel ter Beek, Ann Concannon | 2005-06-14 |
| 6903979 | Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of substrate current | Yuri Mirgorodski, Vladislav Vashchenko, Douglas Brisbin | 2005-06-07 |
| 6903978 | Method of PMOS stacked-gate memory cell programming enhancement utilizing stair-like pulses of control gate voltage | Yuri Mirgorodski, Vladislav Vashchenko | 2005-06-07 |
| 6894881 | ESD protection methods and devices using additional terminal in the diode structures | Vladislav Vashchenko, Ann Concannon | 2005-05-17 |
| 6864581 | Etched metal trace with reduced RF impendance resulting from the skin effect | Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury | 2005-03-08 |
| 6864582 | Semiconductor interconnect and method of providing interconnect using a contact region | Vladislav Vashchenko, Philipp Lindorfer, Andy Strachan, Peter Johnson | 2005-03-08 |
| 6861306 | Method of forming a split-gate memory cell with a tip in the middle of the floating gate | Yuri Mirgorodski | 2005-03-01 |
| 6862720 | Interconnect exhibiting reduced parasitic capacitance variation | — | 2005-03-01 |
| 6862216 | Non-volatile memory cell with gated diode and MOS transistor and method for using such cell | Yuri Mirgorodski, Vladislav Vashchenko | 2005-03-01 |