Issued Patents 2005
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6958266 | Semiconductor device, method of manufacturing same and method of designing same | Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Shigenobu Maeda, Yuuichi Hirano +2 more | 2005-10-25 |
| 6953979 | Semiconductor device, method of manufacturing same and method of designing same | Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Shigenobu Maeda, Yuuichi Hirano +2 more | 2005-10-11 |
| 6933565 | Semiconductor device and method of manufacturing the same | Takuji Matsumoto, Yuuichi Hirano | 2005-08-23 |
| 6914307 | Semiconductor device and method of manufacturing the same | Takashi Ipposhi, Hideki Naruoka, Nobuyoshi Hattori, Shigeto Maegawa, Yasuo Yamaguchi +1 more | 2005-07-05 |
| 6902988 | Method for treating substrates for microelectronics and substrates obtained by said method | Thierry Barge, Bruno Ghyselen, Hideki Naruoka, Junichiro Furihata, Kiyoshi Mitani | 2005-06-07 |
| 6879002 | Semiconductor device having an SOI substrate | Shoichi Miyamoto, Takashi Ipposhi | 2005-04-12 |
| 6875663 | Semiconductor device having a trench isolation and method of fabricating the same | Takashi Ipposhi, Takuji Matsumoto, Shigenobu Maeda | 2005-04-05 |
| 6872979 | Semiconductor substrate with stacked oxide and SOI layers with a molten or epitaxial layer formed on an edge of the stacked layers | Yoshiko Yoshida, Hideki Naruoka, Yasuhiro Kimura, Yasuo Yamaguchi, Yuuichi Hirano | 2005-03-29 |
| 6841400 | Method of manufacturing semiconductor device having trench isolation | Takuji Matsumoto, Mikio Tsujiuchi, Shigenobu Maeda, Yuuichi Hirano, Shigeto Maegawa | 2005-01-11 |