Issued Patents 2005
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6964903 | Method of fabricating a transistor on a substrate to operate as a fully depleted structure | Leonard Forbes | 2005-11-15 |
| 6960821 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction | Leonard Forbes, Alan R. Reinberg | 2005-11-01 |
| 6946700 | Trench DRAM cell with vertical device and buried word lines | — | 2005-09-20 |
| 6946389 | Method of forming buried conductors | Paul A. Farrar | 2005-09-20 |
| 6936886 | High density SRAM cell with latched vertical transistors | Leonard Forbes | 2005-08-30 |
| 6924194 | DRAM technology compatible processor/memory chips | Leonard Forbes, Eugene H. Cloud | 2005-08-02 |
| 6909635 | Programmable memory cell using charge trapping in a gate oxide | Leonard Forbes, Eugene H. Cloud | 2005-06-21 |
| 6891213 | Base current reversal SRAM memory cell and method | — | 2005-05-10 |
| 6887749 | Multiple oxide thicknesses for merged memory and logic applications | Leonard Forbes | 2005-05-03 |
| 6884687 | SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY | — | 2005-04-26 |
| 6861311 | SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY | — | 2005-03-01 |
| 6858504 | Method for forming gate segments for an integrated circuit | — | 2005-02-22 |