Issued Patents 2005
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6965923 | System and method for assigning addresses to memory devices | Robert Norman | 2005-11-15 |
| 6961805 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous reading writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2005-11-01 |
| 6954400 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2005-10-11 |
| 6914813 | Segmented non-volatile memory array with multiple sources having improved source line decode circuitry | Christophe J. Chevallier | 2005-07-05 |
| 6856571 | Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure | Christophe J. Chevallier, Mathew L. Adsitt | 2005-02-15 |
| 6842380 | Method and apparatus for erasing memory | Tz-Yi Liu | 2005-01-11 |