Issued Patents 2005
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6870770 | Method and architecture to calibrate read operations in synchronous flash memory | — | 2005-03-22 |
| 6865111 | Method and architecture to calibrate read operations in synchronous flash memory | — | 2005-03-08 |
| 6865702 | Synchronous flash memory with test code input | — | 2005-03-08 |
| 6862222 | Non-volatile memory device with erase address register | — | 2005-03-01 |
| 6859392 | Preconditioning global bitlines | Ebrahim Abedifard | 2005-02-22 |
| 6851026 | Synchronous flash memory with concurrent write and read operation | — | 2005-02-01 |
| 6847565 | Memory with row redundancy | Ebrahim Abedifard | 2005-01-25 |
| 6845057 | DDR synchronous flash memory with virtual segment architecture | Kevin C. Widmer, Cliff Zitlaw | 2005-01-18 |
| 6842385 | Automatic reference voltage regulation in a memory device | Dumitru Cioaca, Christophe J. Chevallier, Al Vahidimowlavi | 2005-01-11 |
| 6839875 | Method and apparatus for performing error correction on data read from a multistate memory | — | 2005-01-04 |