Issued Patents 2005
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6981083 | Processor virtualization mechanism via an enhanced restoration of hard architected states | Robert Alan Cargnoni, Guy L. Guthrie, William J. Starke | 2005-12-27 |
| 6976148 | Acceleration of input/output (I/O) communication through improved address translation | Robert Alan Cargnoni, Guy L. Guthrie, William J. Starke | 2005-12-13 |
| 6970976 | Layered local cache with lower level cache optimizing allocation mechanism | Leo James Clark, John Steven Dodson, Guy L. Guthrie | 2005-11-29 |
| 6963967 | System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture | Guy L. Guthrie, John Steven Dodson, Derek E. Williams | 2005-11-08 |
| 6944721 | Asynchronous non-blocking snoop invalidation | Guy L. Guthrie | 2005-09-13 |
| 6928524 | Data processing system with naked cache line write operations | Benjiman L. Goodman, Jody B. Joyner | 2005-08-09 |
| 6925551 | Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction | Derek E. Williams | 2005-08-02 |
| 6920521 | Method and system of managing virtualized physical memory in a data processing system | John Steven Dodson, Sanjeev Ghai, Kenneth L. Wright | 2005-07-19 |
| 6920514 | Method, apparatus and system that cache promotion information within a processor separate from instructions and data | Derek E. Williams | 2005-07-19 |
| 6915390 | High speed memory cloning facility via a coherently done mechanism | Benjiman L. Goodman, Jody B. Joyner | 2005-07-05 |
| 6910062 | Method and apparatus for transmitting packets within a symmetric multiprocessor system | Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2005-06-21 |
| 6907494 | Method and system of managing virtualized physical memory in a memory controller and processor system | John Steven Dodson, Sanjeev Ghai, Kenneth L. Wright | 2005-06-14 |
| 6904490 | Method and system of managing virtualized physical memory in a multi-processor system | John Steven Dodson, Sanjeev Ghai, Kenneth L. Wright | 2005-06-07 |
| 6901485 | Memory directory management in a multi-node computer system | John Steven Dodson, James Stephen Fields, Jr. | 2005-05-31 |
| 6898677 | Dynamic software accessibility to a microprocessor system with a high speed memory cloner | Benjiman L. Goodman, Jody B. Joyner | 2005-05-24 |
| 6892283 | High speed memory cloner with extended cache coherency protocols and responses | Benjiman L. Goodman, Jody B. Joyner | 2005-05-10 |
| 6886079 | Dynamic history based mechanism for the granting of exclusive data ownership in a non-uniform memory access (NUMA) computer system | John Steven Dodson, James Stephen Fields, Jr. | 2005-04-26 |
| 6880073 | Speculative execution of instructions and processes before completion of preceding barrier operations | John Steven Dodson, Guy L. Guthrie, Derek E. Williams | 2005-04-12 |
| 6877083 | Address mapping mechanism for behavioral memory enablement within a data processing system | William J. Starke | 2005-04-05 |
| 6874063 | System bus read data transfers with data ordering control bits | Vicente Enrique Chung, Guy L. Guthrie, Jody B. Joyner | 2005-03-29 |
| 6865695 | Robust system bus recovery | Jody B. Joyner, Jerry Don Lewis, Vicente Enrique Chung | 2005-03-08 |
| 6848003 | Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response | James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2005-01-25 |
| 6842847 | Method, apparatus and system for acquiring a plurality of global promotion facilities through execution of an instruction | Derek E. Williams | 2005-01-11 |