Issued Patents 2005
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6980028 | Dedicated input/output first in/first out module for a field programmable gate array | Arunangshu Kundu | 2005-12-27 |
| 6976185 | Delay locked loop for an FPGA architecture | Nikhil Mazumder, Arunangshu Kundu, James D. Joseph, Wayne W. Wong | 2005-12-13 |
| 6946871 | Multi-level routing architecture in a field programmable gate array having transmitters and receivers | Arunangshu Kundu, Venkatesh Narayanan, John McCollum | 2005-09-20 |
| 6891396 | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks | Arunangshu Kundu, Eric A. Sather | 2005-05-10 |
| 6867615 | Dedicated input/output first in/first out module for a field programmable gate array | Arunangshu Kundu | 2005-03-15 |
| 6838899 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array | — | 2005-01-04 |