MY

Masaaki Yamada

KT Kabushiki Kaisha Toshiba: 3 patents #163 of 2,092Top 8%
📍 Tokyo, NJ: #5 of 25 inventorsTop 20%
Overall (2004): #23,863 of 270,089Top 9%
3
Patents 2004

Issued Patents 2004

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
6813756 Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program Mutsunori Igarashi, Masami Murakata, Takashi Mitsuhashi, Fumihiro Minami, Takashi Ishioka 2004-11-02
6792593 Pattern correction method, apparatus, and program Makoto Takashima, Atsuhiko Ikeuchi, Koji Hashimoto, Mutsunori Igarashi 2004-09-14
6779167 Automated wiring pattern layout method Mutsunori Igarashi, Koji Hashimoto, Makoto Takashima, Atsuhiko Ikeuchi 2004-08-17