MI

Mutsunori Igarashi

KT Kabushiki Kaisha Toshiba: 5 patents #69 of 2,092Top 4%
Overall (2004): #7,948 of 270,089Top 3%
5
Patents 2004

Issued Patents 2004

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
6813756 Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program Masami Murakata, Takashi Mitsuhashi, Masaaki Yamada, Fumihiro Minami, Takashi Ishioka 2004-11-02
6792593 Pattern correction method, apparatus, and program Makoto Takashima, Atsuhiko Ikeuchi, Koji Hashimoto, Masaaki Yamada 2004-09-14
6779167 Automated wiring pattern layout method Masaaki Yamada, Koji Hashimoto, Makoto Takashima, Atsuhiko Ikeuchi 2004-08-17
6763508 Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same Takashi Mitsuhashi 2004-07-13
6683336 SEMICONDUCTOR INTEGRATED CIRCUIT, SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECORD MEDIUM FOR STORING PROGRAM OF SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT Hiroshi Tanaka, Kimiyoshi Usami, Takashi Ishikawa, Masahiro Kanazawa, Chiharu Mizuno 2004-01-27