TM

Takashi Mitsuhashi

KT Kabushiki Kaisha Toshiba: 2 patents #303 of 2,092Top 15%
Overall (2004): #39,166 of 270,089Top 15%
2
Patents 2004

Issued Patents 2004

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6813756 Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program Mutsunori Igarashi, Masami Murakata, Masaaki Yamada, Fumihiro Minami, Takashi Ishioka 2004-11-02
6763508 Layout design system, layout design method and layout design program of semiconductor integrated circuit, and method of manufacturing the same Mutsunori Igarashi 2004-07-13