Issued Patents 2004
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6745160 | Verification of scheduling in the presence of loops using uninterpreted symbolic simulation | Pranav Ashar, Subhrajit Bhattacharya, Aarti Gupta | 2004-06-01 |
| 6735744 | Power mode based macro-models for power estimation of electronic circuits | Ganesh Lakshminarayana, Nachiketh Rao Potlapally, Michael Hsiao, Srimat Chakradhar | 2004-05-11 |
| 6694488 | System for the design of high-performance communication architecture for system-on-chips using communication architecture tuners | Ganesh Lakshminarayana, Kanishka Lahiri | 2004-02-17 |