Issued Patents 2004
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6818545 | Low fabrication cost, fine pitch and high reliability solder bump | Jin-Yuan Lee, Ching-Cheng Huang | 2004-11-16 |
| 6815324 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Ching-Cheng Huang, Chuen-Jye Lin, Ming-Ta Lei | 2004-11-09 |
| 6800941 | Integrated chip package structure using ceramic substrate and method of manufacturing the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-10-05 |
| 6798073 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-09-28 |
| 6791192 | Multiple chips bonded to packaging structure with low noise and multiple selectable functions | Bryan Peng | 2004-09-14 |
| 6768208 | Multiple chips bonded to packaging structure with low noise and multiple selectable functions | Bryan Peng | 2004-07-27 |
| 6762115 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-07-13 |
| 6759275 | Method for making high-performance RF integrated circuits | Jin-Yuan Lee | 2004-07-06 |
| 6756295 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-06-29 |
| 6746898 | Integrated chip package structure using silicon substrate and method of manufacturing the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-06-08 |
| 6734563 | Post passivation interconnection schemes on top of the IC chips | Jin-Yuan Lee | 2004-05-11 |
| 6700162 | Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip | Jin-Yuan Lee, Ching-Cheng Huang | 2004-03-02 |
| 6673698 | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers | Jin-Yuan Lee, Ching-Cheng Huang | 2004-01-06 |