Issued Patents 2004
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6818545 | Low fabrication cost, fine pitch and high reliability solder bump | Mou-Shiung Lin, Ching-Cheng Huang | 2004-11-16 |
| 6818495 | Method for forming high purity silicon oxide field oxide isolation region | Min-Hsiung Chiang, Jenn Ming Huang | 2004-11-16 |
| 6809935 | Thermally compliant PCB substrate for the application of chip scale packages | — | 2004-10-26 |
| 6806570 | Thermal compliant semiconductor chip wiring structure for chip scale packaging | Eric Lin | 2004-10-19 |
| 6800941 | Integrated chip package structure using ceramic substrate and method of manufacturing the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-10-05 |
| 6798073 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-09-28 |
| 6784087 | Method of fabricating cylindrical bonding structure | Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo | 2004-08-31 |
| 6762115 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-07-13 |
| 6759275 | Method for making high-performance RF integrated circuits | Mou-Shiung Lin | 2004-07-06 |
| 6756295 | Chip structure and process for forming the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-06-29 |
| 6746898 | Integrated chip package structure using silicon substrate and method of manufacturing the same | Mou-Shiung Lin, Ching-Cheng Huang | 2004-06-08 |
| 6734563 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin | 2004-05-11 |
| 6700162 | Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip | Mou-Shiung Lin, Ching-Cheng Huang | 2004-03-02 |
| 6673698 | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers | Mou-Shiung Lin, Ching-Cheng Huang | 2004-01-06 |