Issued Patents 2004
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6782525 | Wafer process critical dimension, alignment, and registration analysis simulation tool | Mario Garza, George E. Bailey, Travis Brist, Paul G. Filseth | 2004-08-24 |
| 6775818 | Device parameter and gate performance simulation based on wafer image prediction | Kunal N. Taravade, Nadya Strelkova | 2004-08-10 |