Issued Patents 2004
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6825692 | Input buffer for multiple differential I/O standards | Jonathan Chung, In Whan Kim, Philip Pan, Chiakang Sung, Bonnie I. Wang +5 more | 2004-11-30 |
| 6806733 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2004-10-19 |
| 6766505 | Parallel programming of programmable logic using register chains | Gopi Rangan, Khai Nguyen, Chiakang Sung, Xiaobao Wang, In Whan Kim +3 more | 2004-07-20 |
| 6747903 | Configurable decoder for addressing a memory | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang, Khai Nguyen +4 more | 2004-06-08 |
| 6731142 | Circuit for providing clock signals with low skew | Bonnie I. Wang, Chiakang Sung, Khai Nguyen, Joseph Huang, Xiaobao Wang +4 more | 2004-05-04 |
| 6731137 | Programmable, staged, bus hold and weak pull-up for bi-directional I/O | Gopinath Rangan, Chiakang Sung, Xiaobao Wang, Philip Pan, In Whan Kim +4 more | 2004-05-04 |
| 6714044 | Hi-speed parallel configuration of programmable logic | Gopi Rangan, Khai Nguyen, Chiakang Sung, Xiaobao Wang, In Whan Kim +3 more | 2004-03-30 |
| 6686769 | Programmable I/O element circuit for high speed logic devices | Khai Nguyen, Chiakang Sung, Bonnie I. Wang, Joseph Huang, Phillip Pan +4 more | 2004-02-03 |