PS

Peilin Song

CS Cadence Design Systems: 1 patents #23 of 106Top 25%
IBM: 1 patents #1,866 of 5,464Top 35%
📍 Lagrangeville, NY: #7 of 32 inventorsTop 25%
🗺 New York: #1,410 of 9,035 inventorsTop 20%
Overall (2004): #46,151 of 270,089Top 20%
2
Patents 2004

Issued Patents 2004

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6816990 VLSI chip test power reduction Timothy J. Koprowski, Ulrich Baur, Franco Motika 2004-11-09
6728914 Random path delay testing methodology Kevin William McCauley, William V. Huott, Mary P. Kusko, Richard F. Rizzolo, Ulrich Baur +1 more 2004-04-27