Issued Patents 2004
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6808974 | CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions | Heemyong Park, Dominic J. Schepis | 2004-10-26 |
| 6777304 | Method for producing an integrated circuit capacitor | Harold W. Chase, Stephen L. Runyon | 2004-08-17 |
| 6734109 | Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon | Heemyong Park, Jack A. Mandelman | 2004-05-11 |
| 6714476 | Memory array with dual wordline operation | Louis L. Hsu, Rajiv V. Joshi | 2004-03-30 |
| 6713791 | T-RAM array having a planar cell structure and method for fabricating the same | Louis L. Hsu, Rajiv V. Joshi, Dan Moy, Werner Rausch, James A. Culp | 2004-03-30 |
| 6686629 | SOI MOSFETS exhibiting reduced floating-body effects | Werner Rausch, Dominic J. Schepis, Ghavam G. Shahidi | 2004-02-03 |
| 6677645 | Body contact MOSFET | Andres Bryant, Peter E. Cottrell, John J. Ellis-Monaghan, Robert J. Gauthier, Jr., Edward J. Nowak +1 more | 2004-01-13 |