Issued Patents 2004
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6815282 | Silicon on insulator field effect transistor having shared body contact | William R. Dachtera, Werner Rausch | 2004-11-09 |
| 6798688 | Storage array such as a SRAM with reduced power requirements | — | 2004-09-28 |
| 6798682 | Reduced integrated circuit chip leakage and method of reducing leakage | Ching-Te Chuang, Michael Rosenfield | 2004-09-28 |
| 6791886 | SRAM cell with bootstrapped power line | Azeez Bhavnagarwala, Stephen V. Kosonocky | 2004-09-14 |
| 6788112 | High performance dual-stage sense amplifier circuit | Yuen H. Chan, Antonio R. Pelella, John R. Rawlins, Jatinder K. Wadhwa | 2004-09-07 |
| 6788566 | Self-timed read and write assist and restore circuit | Azeez Bhavnagarwala, Stephen V. Kosonocky | 2004-09-07 |
| 6789099 | Sense-amp based adder with source follower evaluation tree | Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy | 2004-09-07 |
| 6778447 | Embedded DRAM system having wide data bandwidth and data transfer data protocol | Louis L. Hsu, Jeremy K. Stephens, Daniel W. Storaska | 2004-08-17 |
| 6751156 | Semiconductor memory system having dynamically delayed timing for high-speed data transfers | Louis L. Hsu | 2004-06-15 |
| 6724225 | Logic circuit for true and complement signal generator | Ruchir Puri | 2004-04-20 |
| 6714476 | Memory array with dual wordline operation | Louis L. Hsu, Fariborz Assaderaghi | 2004-03-30 |
| 6713791 | T-RAM array having a planar cell structure and method for fabricating the same | Louis L. Hsu, Fariborz Assaderaghi, Dan Moy, Werner Rausch, James A. Culp | 2004-03-30 |
| 6683805 | Suppression of leakage currents in VLSI logic and memory circuits | Louis L. Hsu, Azeez Bhavnagarwala | 2004-01-27 |