Issued Patents 2004
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6826733 | Parameter variation tolerant method for circuit design optimization | Xiaoliang Bai, Chandramouli Visweswariah, Philip Neil Strenski | 2004-11-30 |
| 6795951 | Method and system for fault-tolerant static timing analysis | Peter J. Osler | 2004-09-21 |
| 6792582 | Concurrent logical and physical construction of voltage islands for mixed supply voltage designs | John M. Cohn, Alvar A. Dean, David E. Lackey, Thomas Lepsic, Susan K. Lichtensteiger +2 more | 2004-09-14 |
| 6778999 | Method for distributing a set of objects in computer application | — | 2004-08-17 |
| 6751744 | Method of integrated circuit design checking using progressive individual network analysis | Robert J. Allen, John M. Cohn | 2004-06-15 |
| 6718523 | Reduced pessimism clock gating tests for a timing analysis tool | Jeffrey P. Soreff, Neil Ray Vanderschaaf, James D. Warnock | 2004-04-06 |
| 6711719 | Method and apparatus for reducing power consumption in VLSI circuit designs | John M. Cohn, Alvar A. Dean, Amir Farrahi, Thomas Lepsic, Patrick E. Perry +2 more | 2004-03-23 |
| 6687883 | System and method for inserting leakage reduction control in logic circuits | John M. Cohn, Alvar A. Dean, Sebastian T. Ventrone | 2004-02-03 |