Issued Patents 2004
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6763504 | Method for reducing RC parasitics in interconnect networks of an integrated circuit | Vasant Rao, Ravichander Ledalla, Fred Yang | 2004-07-13 |
| 6718523 | Reduced pessimism clock gating tests for a timing analysis tool | David J. Hathaway, Neil Ray Vanderschaaf, James D. Warnock | 2004-04-06 |