Issued Patents 2004
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833307 | Method for manufacturing a semiconductor component having an early halo implant | Chad Weintraub, James F. Buller, Jon D. Cheek | 2004-12-21 |
| 6822260 | Linewidth measurement structure with embedded scatterometry structure | Hormuzdiar E. Nariman | 2004-11-23 |
| 6812506 | Polysilicon linewidth measurement structure with embedded transistor | Hormuzdiar E. Nariman | 2004-11-02 |
| 6801096 | Ring oscillator with embedded scatterometry grate array | Hormuzdiar E. Nariman, James F. Buller | 2004-10-05 |
| 6780686 | Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions | Andy Wei, Mark B. Fuselier | 2004-08-24 |
| 6764908 | Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents | Daniel Kadosh, Qi Xiang, Bin Yu | 2004-07-20 |
| 6737332 | Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same | Mark B. Fuselier, Andy Wei | 2004-05-18 |
| 6727534 | Electrically programmed MOS transistor source/drain series resistance | James F. Buller, Qi Xiang | 2004-04-27 |
| 6727136 | Formation of ultra-shallow depth source/drain extensions for MOS transistors | James F. Buller, David Wu, Akif Sultan | 2004-04-27 |
| 6707106 | Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer | Qi Xiang, James F. Buller | 2004-03-16 |
| 6689671 | Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate | Bin Yu | 2004-02-10 |
| 6674135 | Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric | Jon D. Cheek, Mark I. Gardner | 2004-01-06 |