Issued Patents 2003
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6614078 | Highly latchup-immune CMOS I/O structures | Jian-Hsing Lee, Shui-Hung Chen, Ping Lung Liao | 2003-09-02 |
| 6614693 | Combination erase waveform to reduce oxide trapping centers generation rate of flash EEPROM | Jian-Hsing Lee, Kuo-Reay Peng, Shui-Hung Chen | 2003-09-02 |
| 6582997 | ESD protection scheme for outputs with resistor loading | Jian-Hsing Lee, Shui-Hun Chen | 2003-06-24 |
| 6541824 | Modified source side inserted anti-type diffusion ESD protection device | Jian-Hsing Lee, Shui-Hung Chen, Yi-Hsun Wu | 2003-04-01 |