NT

Naoto Tate

SE Seh-America: 1 patents #11 of 33Top 35%
SC Shin-Etsu Handotai Co.: 1 patents #21 of 67Top 35%
ST S.O.I. Tec Silicon On Insulator Technologies: 1 patents #1 of 7Top 15%
📍 Camas, WA: #16 of 50 inventorsTop 35%
🗺 Washington: #493 of 3,868 inventorsTop 15%
Overall (2003): #50,180 of 273,478Top 20%
2
Patents 2003

Issued Patents 2003

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6596610 Method for reclaiming delaminated wafer and reclaimed delaminated wafer Susumu Kuwabara, Kiyoshi Mitani, Masatake Nakano, Thierry Barge, Christophe Maleville 2003-07-22
6569749 Silicon and oxygen ion co-implanation for metallic gettering in epitaxial wafers Witawat Wijaranakula, Jallepally Ravi 2003-05-27