Issued Patents 2003
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6656805 | METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT | Rajiv Patel, Ravindra M. Kapre | 2003-12-02 |
| 6617251 | Method of shallow trench isolation formation and planarization | Venkatesh P. Gopinth | 2003-09-09 |
| 6586291 | High density memory with storage capacitor | Ruggero Castagnetti | 2003-07-01 |
| 6586814 | Etch resistant shallow trench isolation in a semiconductor wafer | Rajiv Patel, David Chan, Ken Rafftesaeth, Venkatesh P. Gopinath | 2003-07-01 |
| 6569739 | Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers | Venkatesh P. Gopinath | 2003-05-27 |
| 6562729 | Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit | Rajiv Patel, Mohammad Mirabedini | 2003-05-13 |
| 6544829 | Polysilicon gate salicidation | Venkatesh P. Gopinath, Mohammad Mirabedini, Charles E. May | 2003-04-08 |
| 6521549 | METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT | Rajiv Patel, Ravindra M. Kapre | 2003-02-18 |