RP

Rajiv Patel

Lsi Logic: 4 patents #29 of 465Top 7%
📍 San Jose, CA: #157 of 2,756 inventorsTop 6%
🗺 California: #1,459 of 28,521 inventorsTop 6%
Overall (2003): #13,443 of 273,478Top 5%
4
Patents 2003

Issued Patents 2003

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
6656805 METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT Arvind Kamath, Ravindra M. Kapre 2003-12-02
6586814 Etch resistant shallow trench isolation in a semiconductor wafer David Chan, Arvind Kamath, Ken Rafftesaeth, Venkatesh P. Gopinath 2003-07-01
6562729 Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit Arvind Kamath, Mohammad Mirabedini 2003-05-13
6521549 METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT Arvind Kamath, Ravindra M. Kapre 2003-02-18