Issued Patents 2003
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6661254 | Programmable interconnect circuit with a phase-locked loop | Jinghui Zhu, Kuang Chi, Chienkuang Chen | 2003-12-09 |
| 6653860 | Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures | Xiaojie He, Claudia A. Stanley, Larry R. Metzger, Chong M. Lee | 2003-11-25 |
| 6653861 | Multi-level routing structure for a programmable interconnect circuit | Jinghui Zhu | 2003-11-25 |
| 6650141 | High speed interface for a programmable interconnect circuit | Jinghui Zhu, Kuang Chi, Chienkuang Chen | 2003-11-18 |
| 6650142 | Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use | Fabiano Fontana, Gilles Bosco | 2003-11-18 |
| 6621298 | Variable grain architecture for FPGA integrated circuits | Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran | 2003-09-16 |
| 6590415 | Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources | Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2003-07-08 |
| 6567969 | Configurable logic array including lookup table means for generating functions of different numbers of input terms | Michael J. Wright, Ju Shen | 2003-05-20 |
| 6531890 | Programmable optimized-distribution logic allocator for a high-density complex PLD | Bradley A. Sharpe-Geisler, Nicholas A. Schmitz | 2003-03-11 |
| 6526558 | Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources | Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2003-02-25 |