Issued Patents 2003
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6636978 | Rescheduling data input and output commands for bus synchronization by using digital latency shift detection | L. Brian Ji, John M. Ross | 2003-10-21 |
| 6587388 | Method and apparatus for reducing write operation time in dynamic random access memories | Sang Hoo Dhong, Hwa-Joon Oh | 2003-07-01 |
| 6552944 | Single bitline direct sensing architecture for high speed memory device | John A. Fifield, Wing K. Luk, Jeremy K. Stephens, Daniel W. Storaska | 2003-04-22 |
| 6542973 | Integrated redundancy architecture system for an embedded DRAM | Louis L. Hsu, Li-Kong Wang, Gregory J. Fredeman | 2003-04-01 |
| 6522171 | Method of reducing sub-threshold leakage in circuits during standby mode | David R. Hanson, Gerhard Mueller | 2003-02-18 |
| 6519174 | Early write DRAM architecture with vertically folded bitlines | Sang Hoo Dhong | 2003-02-11 |
| 6512683 | System and method for increasing the speed of memories | Louis L. Hsu, Li-Kong Wang | 2003-01-28 |