Issued Patents 2003
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6600959 | Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays | Paula Kristine Coulman, Brian Flachs, Harm Peter Hofstee, Jaehong Park, Stephen Douglas Posluszny +2 more | 2003-07-29 |
| 6594679 | Leading-zero anticipator having an independent sign bit determination module | Kyung Tek Lee, Kevin John Nowka | 2003-07-15 |
| 6587388 | Method and apparatus for reducing write operation time in dynamic random access memories | Toshiaki Kirihata, Hwa-Joon Oh | 2003-07-01 |
| 6584485 | 4 to 2 adder | Naoaki Aoki, Nobuo Kojima, Ohsang Kwon | 2003-06-24 |
| 6574698 | Method and system for accessing a cache memory within a data processing system | Joel A. Silberman | 2003-06-03 |
| 6535041 | Strobe circuit keeper arrangement providing reduced power consumption | Robert J. Bucki, Jeffrey Herbert Fischer, Joel A. Silberman, Osamu Takahashi | 2003-03-18 |
| 6519174 | Early write DRAM architecture with vertically folded bitlines | Toshiaki Kirihata | 2003-02-11 |
| 6510093 | Method and apparatus for cycle time reduction in a memory system using alternating reference cells and isolated sense lines | Hwa-Joon Oh | 2003-01-21 |