WK

Wei-Lun Kao

CS Cadence Design Systems: 1 patents #17 of 82Top 25%
SP Silicon Perspective: 1 patents #2 of 8Top 25%
📍 Cupertino, CA: #140 of 688 inventorsTop 25%
🗺 California: #4,287 of 28,521 inventorsTop 20%
Overall (2003): #37,162 of 273,478Top 15%
2
Patents 2003

Issued Patents 2003

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6651235 Scalable, partitioning integrated circuit layout system Wei-Jin Dai, Kit Lam Cheong, Hsi-Chuan Chen 2003-11-18
6519749 Integrated circuit partitioning placement and routing system Ping Chao, Wei-Jin Dai, Mitsuru Igusa, Jia-Jye Shen 2003-02-11