WD

Wei-Jin Dai

SP Silicon Perspective: 2 patents #1 of 8Top 15%
CS Cadence Design Systems: 1 patents #17 of 82Top 25%
📍 Cupertino, CA: #72 of 688 inventorsTop 15%
🗺 California: #2,413 of 28,521 inventorsTop 9%
Overall (2003): #19,543 of 273,478Top 8%
3
Patents 2003

Issued Patents 2003

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
6651235 Scalable, partitioning integrated circuit layout system Kit Lam Cheong, Hsi-Chuan Chen, Wei-Lun Kao 2003-11-18
6578183 Method for generating a partitioned IC layout Kit Lam Cheong, Hsi-Chuan Chen, Patrick John Eichenseer 2003-06-10
6519749 Integrated circuit partitioning placement and routing system Ping Chao, Mitsuru Igusa, Wei-Lun Kao, Jia-Jye Shen 2003-02-11