KC

Kit Lam Cheong

CS Cadence Design Systems: 1 patents #17 of 82Top 25%
SP Silicon Perspective: 1 patents #2 of 8Top 25%
📍 Palo Alto, CA: #189 of 969 inventorsTop 20%
🗺 California: #4,287 of 28,521 inventorsTop 20%
Overall (2003): #56,652 of 273,478Top 25%
2
Patents 2003

Issued Patents 2003

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6651235 Scalable, partitioning integrated circuit layout system Wei-Jin Dai, Hsi-Chuan Chen, Wei-Lun Kao 2003-11-18
6578183 Method for generating a partitioned IC layout Wei-Jin Dai, Hsi-Chuan Chen, Patrick John Eichenseer 2003-06-10