SV

Shekaripuram V. Venkatesh

CS Cadence Design Systems: 1 patents #6 of 34Top 20%
📍 Los Altos, CA: #157 of 415 inventorsTop 40%
🗺 California: #8,284 of 26,763 inventorsTop 35%
Overall (2002): #116,581 of 266,432Top 45%
1
Patents 2002

Issued Patents 2002

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6442739 System and method for timing abstraction of digital logic circuits Robert J. Palermo, Karem A. Sakallah, Mohammad Mortazavi 2002-08-27