Issued Patents 2002
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6498396 | Semiconductor chip scale package and ball grid array structures | — | 2002-12-24 |
| 6486493 | Semiconductor integrated circuit device having hierarchical test interface circuit | Hiroki Shimano | 2002-11-26 |
| 6483139 | Semiconductor memory device formed on semiconductor substrate | Hiroki Shimano | 2002-11-19 |
| 6477108 | Semiconductor device including memory with reduced current consumption | Hiroki Shimano | 2002-11-05 |
| 6459113 | Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells | Toshinori Morihara, Hiroki Shimano | 2002-10-01 |
| 6456560 | Semiconductor integrated circuit device with test interface circuit for performing test on embedded memory from outside | Hiroki Shimano | 2002-09-24 |
| 6452859 | Dynamic semiconductor memory device superior in refresh characteristics | Hiroki Shimano, Katsumi Dosaka | 2002-09-17 |
| 6449204 | DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRESH INTERVAL | Hiroki Shimano, Takeshi Fujino, Takeshi Hashizume | 2002-09-10 |
| 6448602 | Semiconductor memory device with improved arrangement of memory blocks and peripheral circuits | Narumi Sakashita | 2002-09-10 |
| 6442078 | Semiconductor memory device having structure implementing high data transfer rate | — | 2002-08-27 |
| 6418075 | Semiconductor merged logic and memory capable of preventing an increase in an abnormal current during power-up | Hiroki Shimano, Yasuhiro Ishizuka, Seizou Furubeppu, Hiroki Sugano | 2002-07-09 |
| 6418067 | Semiconductor memory device suitable for merging with logic | Naoya Watanabe, Akira Yamazaki, Takeshi Fujino, Isamu Hayashi, Hideyuki Noda | 2002-07-09 |
| 6414890 | Semiconductor memory device capable of reliably performing burn-in test at wafer level | Hiroki Shimano | 2002-07-02 |
| 6414883 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Shigeki Tomishima +1 more | 2002-07-02 |
| 6404684 | Test interface circuit and semiconductor integrated circuit device including the same | Hiroki Shimano | 2002-06-11 |
| 6404056 | Semiconductor integrated circuit | Shigehiro Kuge, Masaki Tsukude, Kazuyasu Fujishima | 2002-06-11 |
| 6400628 | Semiconductor memory device | Katsumi Dosaka, Hiroki Shimano, Hiroki Sugano | 2002-06-04 |
| 6400625 | Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester | Hiroki Shimano, Katsumi Dosaka | 2002-06-04 |
| 6388329 | Semiconductor integrated circuit having three wiring layers | Shigehiro Kuge | 2002-05-14 |
| 6388929 | Semiconductor memory device performing redundancy repair based on operation test and semiconductor integrated circuit device having the same | Hiroki Shimano | 2002-05-14 |
| 6377483 | Semiconductor memory device having improved memory cell and bit line pitch | Hiroki Shimano, Toshinori Morihara | 2002-04-23 |
| 6377508 | Dynamic semiconductor memory device having excellent charge retention characteristics | Shigeki Tomishima | 2002-04-23 |
| 6373321 | CMOS semiconductor device | Tadaaki Yamauchi | 2002-04-16 |
| 6341098 | Semiconductor integrated circuit device having hierarchical power source arrangement | Tadato Yamagata, Masaki Tsukude | 2002-01-22 |
| 6337506 | Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area | Fukashi Morishita, Teruhiko Amano, Tetsushi Tanizaki, Takeshi Fujino, Takahiro Tsuruda +2 more | 2002-01-08 |