Issued Patents 2002
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501326 | Semiconductor integrated circuit | Nobuyuki Fujii, Akira Yamazaki, Yasuhiko Taito, Mako Okamoto | 2002-12-31 |
| 6483357 | Semiconductor device reduced in through current | Hiroshi Kato | 2002-11-19 |
| 6472926 | Internal voltage generation circuit | Yasuhiko Taito, Akira Yamazaki, Mako Kobayashi, Mihoko Akiyama, Nobuyuki Fujii | 2002-10-29 |
| 6434078 | Semiconductor device allowing external setting of internal power supply voltage generated by a voltage down converter at the time of testing | — | 2002-08-13 |
| 6429729 | Semiconductor integrated circuit device having circuit generating reference voltage | Mako Kobayashi, Mihoko Akiyama, Yasuhiko Taito, Akira Yamazaki, Nobuyuki Fujii | 2002-08-06 |
| 6424134 | Semiconductor integrated circuit device capable of stably generating internal voltage independent of an external power supply voltage | Akira Yamazaki, Yasuhiko Taito, Nobuyuki Fujii, Mihoko Akiyama, Mako Kobayashi | 2002-07-23 |
| 6424579 | Semiconductor memory device with internal power supply potential generation circuit | Mihoko Akiyama, Akira Yamazaki, Yasuhiko Taito, Nobuyuki Fujii, Mako Okamoto | 2002-07-23 |
| 6414881 | Semiconductor device capable of generating internal voltage effectively | Nobuyuki Fujii, Akira Yamazaki, Yasuhiko Taito, Mihoko Akiyama, Mako Kobayashi | 2002-07-02 |
| 6407538 | Voltage down converter allowing supply of stable internal power supply voltage | Mitsuya Kinoshita | 2002-06-18 |
| 6392472 | Constant internal voltage generation circuit | Mako Kobayashi | 2002-05-21 |
| 6385117 | Negative voltage generating circuit with high control responsiveness which can be formed using transistor with low breakdown voltage and semiconductor memory device including the same | — | 2002-05-07 |
| 6373763 | Semiconductor memory provided with data-line equalizing circuit | Yasuhiko Taito, Akira Yamazaki, Nobuyuki Fujii, Mako Okamoto | 2002-04-16 |
| 6337506 | Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area | Teruhiko Amano, Kazutami Arimoto, Tetsushi Tanizaki, Takeshi Fujino, Takahiro Tsuruda +2 more | 2002-01-08 |