Issued Patents 2002
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6483156 | Double planar gated SOI MOSFET structure | James W. Adkisson, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson +1 more | 2002-11-19 |
| 6420746 | Three device DRAM cell with integrated capacitor and local interconnect | Randy W. Mann, Jeffrey H. Oppold | 2002-07-16 |
| 6394638 | Trench isolation for active areas and first level conductors | Edward W. Sengle, Mark D. Jaffe, Daniel N. Maynard, Mark A. Lavin, Eric J. White | 2002-05-28 |
| 6373095 | NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area | James S. Nakos | 2002-04-16 |
| 6344381 | Method for forming pillar CMOS | Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman | 2002-02-05 |
| 6339015 | Method of fabricating a non-volatile semiconductor device | James S. Nakos | 2002-01-15 |