GG

Guy L. Guthrie

IBM: 45 patents #4 of 5,400Top 1%
🗺 Texas: #3 of 8,590 inventorsTop 1%
Overall (2002): #26 of 266,432Top 1%
45
Patents 2002

Issued Patents 2002

Showing 26–45 of 45 patents

Patent #TitleCo-InventorsDate
6397300 High performance store instruction management via imprecise local cache update mechanism Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson 2002-05-28
6397298 Cache memory having a programmable cache replacement scheme Ravi Kumar Arimilli, John Steven Dodson 2002-05-28
6393528 Optimized cache allocation algorithm for multiple speculative requests Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, John Steven Dodson, James Stephen Fields, Jr. 2002-05-21
6385694 High performance load instruction management via system bus with explicit register load and/or cache reload protocols Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson 2002-05-07
6385702 High performance multiprocessor system with exclusive-deallocate cache state Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke 2002-05-07
6374333 Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke 2002-04-16
6360297 System bus read address operations with data ordering preference hint bits for vertical caches Ravi Kumar Arimilli, Vicente Enrique Chung, Jody B. Joyner 2002-03-19
6360299 Extended cache state with prefetched stream ID information Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, John Steven Dodson, James Stephen Fields, Jr. 2002-03-19
6353875 Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner, Jerry Don Lewis 2002-03-05
6349367 Method and system for communication in which a castout operation is cancelled in response to snoop responses Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner, Jerry Don Lewis 2002-02-19
6349369 Protocol for transferring modified-unsolicited state during data intervention Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke 2002-02-19
6349360 System bus read address operations with data ordering preference hint bits Ravi Kumar Arimilli, Vicente Enrique Chung, Jody B. Joyner 2002-02-19
6345343 Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke 2002-02-05
6345344 Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke 2002-02-05
6345342 Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, William J. Starke 2002-02-05
6343347 Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner, Jerry Don Lewis 2002-01-29
6343344 System bus directory snooping mechanism for read/castout (RCO) address transaction Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner, Jerry Don Lewis 2002-01-29
6338124 Multiprocessor system bus with system controller explicitly updating snooper LRU information Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner, Jerry Don Lewis 2002-01-08
6338119 Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performance Gary D. Anderson, Ronald Xavier Arroyo, Bradly G. Frey 2002-01-08
6336169 Background kill system bus transaction to optimize coherency transactions on a multiprocessor system bus Ravi Kumar Arimilli, James S. Fields, Jr. 2002-01-01