Issued Patents 2002
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6495399 | Method of vacuum packaging a semiconductor device assembly | Ting Cheong Ang, Duay Ing Ong, Sang Yee Loong | 2002-12-17 |
| 6492726 | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection | Ying-Keung Leung, Sang Yee Loong, Ting Cheong Ang | 2002-12-10 |
| 6486515 | ESD protection network used for SOI technology | Song Jun, Ting Cheong Ang, Sang Yee Loong | 2002-11-26 |
| 6465296 | Vertical source/drain contact semiconductor | Ting Cheong Ang, Sang Yee Loong, Puay Ing Ong | 2002-10-15 |
| 6455384 | Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers | Ting Cheong Ang, Jun Song, Xing Yu | 2002-09-24 |
| 6416909 | Alternating phase shift mask and method for fabricating the alignment monitor | Ting Cheong Ang, Swee Hong Choo, Sang Yee Loong | 2002-07-09 |
| 6406994 | Triple-layered low dielectric constant dielectric dual damascene approach | Ting Cheong Ang, Yee Chong Wong, Sang Yee Loong | 2002-06-18 |
| 6406948 | Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate | Song Jun, Ting Cheong Ang, Sang Yee Loong | 2002-06-18 |
| 6399431 | ESD protection device for SOI technology | Jun Song, Ting Cheong Ang, Sang Yee Loong | 2002-06-04 |
| 6376319 | Process to fabricate a source-drain extension | Ting Cheong Ang, Jun Song, Xing Yu | 2002-04-23 |
| 6376379 | Method of hard mask patterning | Ting Cheong Ang, Jun Song, Sang Yee Loong | 2002-04-23 |