Issued Patents 2002
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6449756 | Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design | Sharad Malik, Eric McCaughrin, Abhijeet Chakraborty, Douglas B. Boyle | 2002-09-10 |
| 6442743 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Sharad Malik, Feroze P. Taraporevala, Abhijeet Chakraborty, Gary K. Yeap +4 more | 2002-08-27 |
| 6385760 | System and method for concurrent placement of gates and associated wiring | Majid Sarrafzadeh, Gary K. Yeap, Feroze P. Taraporevala, Tong Gao, Douglas B. Boyle | 2002-05-07 |
| 6367051 | System and method for concurrent buffer insertion and placement of logic gates | Sharad Malik, Emre Tuncer, Abhijeet Chakraborty, Satyamurthy Pullela, Altan Odabasioglu +1 more | 2002-04-02 |