FT

Feroze P. Taraporevala

MS Monterey Design Systems: 2 patents #5 of 20Top 25%
📍 San Jose, CA: #402 of 2,494 inventorsTop 20%
🗺 California: #3,859 of 26,763 inventorsTop 15%
Overall (2002): #66,104 of 266,432Top 25%
2
Patents 2002

Issued Patents 2002

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6442743 Placement method for integrated circuit design using topo-clustering Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Abhijeet Chakraborty, Gary K. Yeap +4 more 2002-08-27
6385760 System and method for concurrent placement of gates and associated wiring Lawrence Pileggi, Majid Sarrafzadeh, Gary K. Yeap, Tong Gao, Douglas B. Boyle 2002-05-07