Issued Patents 2002
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6500729 | Method for reducing dishing related issues during the formation of shallow trench isolation structures | Arun K. Nanda, Ankineedu Velaga | 2002-12-31 |
| 6498080 | Transistor fabrication method | Taeho Kook, Avinoam Kornblit | 2002-12-24 |
| 6482694 | Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers | Charles Walter Pearce | 2002-11-19 |
| 6472304 | Wire bonding to copper | Sailesh Mansinh Merchant | 2002-10-29 |
| 6455418 | Barrier for copper metallization | Siddhartha Bhowmik, Sailesh Mansinh Merchant | 2002-09-24 |
| 6445043 | Isolated regions in an integrated circuit | — | 2002-09-03 |
| 6426263 | Method for making a merged contact window in a transistor to electrically connect the gate to either the source or the drain | — | 2002-07-30 |
| 6417087 | Process for forming a dual damascene bond pad structure over active circuitry | William T. Cochran, Yehuda Smooha | 2002-07-09 |
| 6387772 | Method for forming trench capacitors in SOI substrates | Charles Walter Pearce, Pradip K. Roy | 2002-05-14 |
| 6384452 | Electrostatic discharge protection device with monolithically formed resistor-capacitor portion | Yehuda Smooha | 2002-05-07 |
| 6365469 | Method for forming dual-polysilicon structures using a built-in stop layer | Michael J. Kelly | 2002-04-02 |
| 6365327 | Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit | Sailesh Mansinh Merchant | 2002-04-02 |
| 6358785 | Method for forming shallow trench isolation structures | Arun K. Nanda, Ankineedu Velaga | 2002-03-19 |
| 6348393 | Capacitor in an integrated circuit and a method of manufacturing an integrated circuit | Sailesh Mansinh Merchant | 2002-02-19 |