Issued Patents 1997
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5689680 | Cache memory system and method for accessing a coincident cache with a bit-sliced architecture | Bruce Ernest Whittaker, Saul Barajas | 1997-11-18 |
| 5644733 | Dual coupled partitionable networks providing arbitration logic for managed access to commonly shared busses | Russell Lee Marrash, Gary C. Whitlock, Kha Nguyen | 1997-07-01 |
| 5642486 | "Invalidation queue with ""bit-sliceability""" | Bruce Ernest Whittaker, Saul Barajas | 1997-06-24 |
| 5598551 | Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles | Saul Barajas, Bruce Ernest Whittaker, Keith S. Saldanha | 1997-01-28 |