Issued Patents 1997
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5703499 | Address bit latching input circuit | Koichi Abe | 1997-12-30 |
| 5615156 | Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines | Hiroyuki Yoshida, Shigeki Numaga, Kiyoshi Nakai, Yukihide Suzuki | 1997-03-25 |