Issued Patents 1997
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5625234 | Semiconductor memory device with bit line and select line arrangement maintaining parasitic capacitance in equilibrium | Hiroyuki Yoshida | 1997-04-29 |
| 5615156 | Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines | Hiroyuki Yoshida, Takashi Inui, Shigeki Numaga, Kiyoshi Nakai | 1997-03-25 |
| 5598373 | Semiconductor memory system | Shoji Wada, Kanehide Kenmizaki, Masaya Muranaka, Masahiro Ogata, Hidetomo Aoyagi +8 more | 1997-01-28 |