Issued Patents 1997
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5696959 | Memory store from a selected one of a register pair conditional upon the state of a selected status bit | Karl M. Guttag, Sydney W. Poland | 1997-12-09 |
| 5696954 | Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1997-12-09 |
| 5696913 | Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor | Robert J. Gove, Karl M. Guttag, Nicholas Ing-Simmons | 1997-12-09 |
| 5651127 | Guided transfers with variable stepping | Robert J. Gove, Karl M. Guttag, Christopher Jensen Read, Iain Robertson, Nicholas Ing Simmons | 1997-07-22 |
| 5640578 | Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section | Nicholas Ing-Simmons, Karl M. Guttag, Robert J. Gove, Jeremiah E. Golston, Christopher Jensen Read +1 more | 1997-06-17 |
| 5634065 | Three input arithmetic logic unit with controllable shifter and mask generator | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1997-05-27 |
| 5613146 | Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors | Robert J. Gove, Nicholas Ing-Simmons, Karl M. Guttag | 1997-03-18 |
| 5606677 | Packed word pair multiply operation forming output including most significant bits of product and other bits of one input | Christopher Jensen Read | 1997-02-25 |
| 5606520 | Address generator with controllable modulo power of two addressing capability | Robert J. Gove, Karl M. Guttag, Nicholas Ing-Simmons | 1997-02-25 |
| 5603049 | Bus system servicing plural module requestors with module access identification known to system user | — | 1997-02-11 |
| 5600847 | Three input arithmetic logic unit with mask generator | Karl M. Guttag, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1997-02-04 |
| 5592405 | Multiple operations employing divided arithmetic logic unit and multiple flags register | Robert J. Gove, Karl M. Guttag, Nicholas Ing-Simmons | 1997-01-07 |