Issued Patents 1997
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5701507 | Architecture of a chip having multiple processors and multiple memories | Walt C. Bonneau, Jr., Robert J. Gove | 1997-12-23 |
| 5696959 | Memory store from a selected one of a register pair conditional upon the state of a selected status bit | Sydney W. Poland, Keith Balmer | 1997-12-09 |
| 5696954 | Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1997-12-09 |
| 5696913 | Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor | Robert J. Gove, Keith Balmer, Nicholas Ing-Simmons | 1997-12-09 |
| 5694348 | Method apparatus and system for correlation | Christopher Jensen Read | 1997-12-02 |
| 5673407 | Data processor having capability to perform both floating point operations and memory access in response to a single instruction | Sydney W. Poland, Christopher Jensen Read, Robert J. Gove, Michael C. Gill, Nicholas Ing Simmons +2 more | 1997-09-30 |
| 5651127 | Guided transfers with variable stepping | Robert J. Gove, Keith Balmer, Christopher Jensen Read, Iain Robertson, Nicholas Ing Simmons | 1997-07-22 |
| 5644524 | Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive or | Jerry R. Van Aken, Sydney W. Poland | 1997-07-01 |
| 5640578 | Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section | Keith Balmer, Nicholas Ing-Simmons, Robert J. Gove, Jeremiah E. Golston, Christopher Jensen Read +1 more | 1997-06-17 |
| 5634065 | Three input arithmetic logic unit with controllable shifter and mask generator | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1997-05-27 |
| 5613146 | Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors | Robert J. Gove, Keith Balmer, Nicholas Ing-Simmons | 1997-03-18 |
| 5606520 | Address generator with controllable modulo power of two addressing capability | Robert J. Gove, Keith Balmer, Nicholas Ing-Simmons | 1997-02-25 |
| 5600847 | Three input arithmetic logic unit with mask generator | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1997-02-04 |
| 5596519 | Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR | Jerry R. Van Aken, Sydney W. Poland | 1997-01-21 |
| 5596767 | Programmable data processing system and apparatus for executing both general purpose instructions and special purpose graphic instructions | Kevin C. McDonough, Sergio Maggi | 1997-01-21 |
| 5596763 | Three input arithmetic logic unit forming mixed arithmetic and boolean combinations | Richard Simpson, Brendan Walsh | 1997-01-21 |
| 5592405 | Multiple operations employing divided arithmetic logic unit and multiple flags register | Robert J. Gove, Keith Balmer, Nicholas Ing-Simmons | 1997-01-07 |