Issued Patents 1997
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5675168 | Unsymmetrical MOS device having a gate insulator area offset from the source and drain areas, and ESD protection circuit including such a MOS device | Kyoji Yamashita, Shinji Odanaka, Akira Hiroki, Isao Miyanaga, Atsushi Hori | 1997-10-07 |
| 5610430 | Semiconductor device having reduced gate overlapping capacitance | Kyoji Yamashita, Shinji Odanaka, Hiroyuki Umimoto | 1997-03-11 |