Issued Patents 1997
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5663888 | Redesign of sequential circuits to reduce clock period | — | 1997-09-02 |
| 5657240 | Testing and removal of redundancies in VLSI circuits with non-boolean primitives | Steven G. Rothweiler, Vishwani D. Agrawal | 1997-08-12 |