Issued Patents 1997
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5664149 | Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol | Marvin W. Martinez, Jr., Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1997-09-02 |
| 5644741 | Processor with single clock decode architecture employing single microROM | Mark W. Hervin, Steven C. McMahan, Raul A. Garibay, Jr. | 1997-07-01 |
| 5632037 | Microprocessor having power management circuitry with coprocessor support | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 1997-05-20 |
| 5630143 | Microprocessor with externally controllable power management | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 1997-05-13 |
| 5630149 | Pipelined processor with register renaming hardware to accommodate multiple size registers | — | 1997-05-13 |
| 5596731 | Single clock bus transfers during burst and non-burst cycles | Marvin W. Martinez, Jr. | 1997-01-21 |